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AMD says there's no FSB in Athlon 64s, (huh?)

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c627627

c(n*199780) Senior Member
Joined
Feb 18, 2002
AMD FAQ:
Q: What is the front-side bus frequency of the AMD Athlon 64 processor?
A: In the AMD Athlon 64 processor, the front-side bus has been replaced by a dedicated memory bus and a HyperTransport technology link. The HyperTransport link operates at a frequency of up to 1600MHz.


"has been replaced" ?


Maxvla said:
ok this whole thread is confusing. when i overclock my A64 rig the pci goes up as well as the memory. i'm thinking that there really is a FSB which is the board speed with dividers for the agp/pci (or locks) the LDT or hypertransport is multiplied off of the fsb stock is 200x3 = 600 for the NF3 150 and 200x4 = 800 for the Via K8 chipset. when the 'fsb' is raised the LDT also raises.

i don't really believe amd when they say there is no fsb as we know it (board speed plus dividers). if there were truly no FSB and everything was 'linked' seperately we should be able to overclock each part of the board seperately. the ram seperate of the pci bus and LDT, and so forth, but this has proven not to be the case.

The 'confusing' thread in q:
http://www.ocforums.com/vb/vb/showthread.php?s=&postid=2446189
 
As I understand it the FSB BUS is gone. But a FSB clock isn't because it is needed to drive the CPU. You need to have one to base the multiplier off of. In a PCI/AGP lock (if your not using asyncronus) you can based the speed off of the FSB clock/CPU clock, or hypertransport clock. In some NF3s it is off of the FSB clock (causing yall to complain), while others it is the HT bus. http://www.lostcircuits.com/motherboard/a64_oc/2.shtml it says that they tried to increase the HT speed and they didn't affect CPU MHZ one bit. So there has to be another clock signle used. Probably the FSB clock, now renamed CPU clock. It seems to me that the HT clock is a multipler of the of CPU clock on teh VIAs, but is independent on the NF3. Anyways, the 2 clocks are different, they are asyncrounus. But some Chipsets like to derive the HT from the CPU CLK causing problem.


I haven't verified this with datasheets but I will and later post my results.
 
hey bulk. can you rephrase that? i didn't understand a word of what you said. lol :D
 
It sounds to me like he's saying "this is just another example of the inefficiencies found in the first generations of a new technology and thus it serves as proof that current chipsets and motherboards for these processors still need to get a few things worked out as far as stability goes".

Plus, nobody is promising anything as far as overclocking goes on the new architecture, either... that'll take some time before you can start getting chipsets and motherboards more optimized for things such as raising 'FSB' speeds.
 
Yeah, I think I kinda get it...but I would appreciate clarification as well.

You're saying the the A64 uses two independent clocks? Like...a single memory clock and a different asychnronous CPU clock?
 
There is no FSB, because the purpose of a FSB is to link the northbridge to the CPU. Since the NB is integrated into the CPU, there is no real FSB. But as for overclocking affecting the PCI/AGP, that is due to the Bus (Hypertransport Bus???) between the CPU/NB and the Southbridge. Since that bus is higher speed than normal (when overclocking), then the speed at which the SB works is higher also. The PCI runs off of the SB, so therefore is running faster than 33Mhz (when oveclocking).
 
ok so FSB technically is only to connect the chip to the NB?

if so then we need to come up with another term.. perhaps Board Bus meaning the speed the board is running at. i'm not buying any of this seperated stuff. the board runs at a certain speed (200mhz) and there are dividers for pci and agp. whenever this board bus is raised not only does the ram raise, the agp/pci and HT bus raise as well. that right there proves it is all connected.
 
ok so FSB technically is only to connect the chip to the NB?

Correct, both the FSB and the FSB clock are gone. They just created a cool new name for technolgy called " HyperTransport", a REALLLY fast "fsb".

Now since there is no "Northbridge" or a FSB, all the HyperTransport is doing is connecting the RAM to the CPU/NB via HyperTransport to create a "dedicated memory bus"

Hope that helped.

Adam
 
Do all present and future 64s have 1600 MHz HyperTransport bus?

We know there are 333 FSB and 400 FSB Bartons. Using semantics of your choice, what's different between present & future 64s other than:
-multiplier
-Single vs. dual channel
-0.13µ vs. 90nm
-cache size

http://www.c627627.com/AMD/AthlonXP/
(scroll down)

What's the Paris and Palermo architecture like? HyperTransport bus?
 
The hypertransport bus is up to 16 bits wide and operates at 800MHz. Since you have two channels (one in each direction) it would be more appropriate to say that you have a total of 32bits operating at 800MHz than to say that you are running at 1600MHz.

The upcoming 939 Athlon 64's are supposed to get an upgrade from 800MHz 16 bit Hypertransport to 1GHz 16 bit hypertransport.

There are two REALLY BIG advantages of the hypertransport bus:

1. With Opterons, the additional hypertransport links allow direct connection from CPU to CPU without any external core logic silicon. This has HUGE implications for the move to mult-core cpus.

2. The transition to PCI express will be very easy since both PCI express and HyperTransport are high-speed serialized busses, a relatively simple bridge is all that will be needed.
 
Thanks Graphic67.

Since newegg is using '1600 MHz' as a figure for 754 Athlon 64 chips, would this then mean that it can be assumed that they intend to advertize the upcoming 939 Athlon 64s as having a '2000 MHz' HyperTransport bus?

What was the HyperTransport bus for Socket 940 Athlon FX?

Wouldn't socket 940 and socket 939 have the same HyperTransport bus?
 
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The change to the hypertransport bus speed is an evolutionary change that will appear with the 939 pin release (and I expect it to appear on the 754 pin cpu's sometime later too for budget and notebook applications). Since 940 will return to being the server option, it is less likely that we will be seeing a migration to the higher speed hypertransport bus as quickly.
 
?
Current Socket 754 Athlon 64 and Socket 940 Athlon FX have no hypertransport bus?

What do they have if not 'FSB' (according to AMD FAQ)?

Are all the vendors advertizing the current CPUs as having hypertransport bus incorrect?
 
c627627 said:
?
Current Socket 754 Athlon 64 and Socket 940 Athlon FX have no hypertransport bus?

What do they have if not 'FSB' (according to AMD FAQ)?

Are all the vendors advertizing the current CPUs as having hypertransport bus incorrect?

Sorry, my previous post should have read:

The change to the HIGHER hypertransport bus speed is an evolutionary change that will appear with the 939 pin release...

It is apparent that there is some of what Scott Adams (of Dilbert fame) referred to once as a "Paradigm shifting without a clutch" at work here.

Older cpus have a core which is tied to a communications bus which are tied tighly together by the speed of the bus. This "front side bus" was even more critical because the memory and all I/O functions were restricted by it.

By incorporating most (but not all) traditional front side bus functions into the cpu, there is much greater flexibility. The cpu core is no longer tied to a rigid communications bus, but rather to the memory bus as a matter of convenience. The hypertransport bus is more like 'firewire on steroids' (no actual relation to IEEE1394) than what you are likely used to thinking of as a front side bus.

If it makes it any easier, think of the AMD cpu's as having TWO front side busses: One 800MHz bus 16bits wide in each direction (for AGP and other I/O) and the second memory bus operating at ddr400 speed. As far as cpu core speed is concerned, the memory bus is in control. The hypertransport bus, as a serialized bus does not influence the speed of the core, but rather the data throughput of all the vital non-memory I/O in your system. Both busses are important, but they are not as easy to fit into neat little packets of marketing hype.
 
I think we're making progress and I thank you for that. Please correct the following:

Instead of the old FSB Front Side Bus, we now have

1. Separate two directional 800 MHz bus (for AGP and other I/O). This is called a HyperTransport bus and is sometimes marketed as a 1600 MHz HyperTransport bus instead of the two directional 800 MHz HyperTransport bus.

2. Separate memory bus operating at PC3200 DDR400 speed (of 400 MHz).


It is the the memory bus and not the HyperTransport bus that is affected by overclocking?

What is the HyperTransport bus for Opteron 140, 142, 144, 146, 148 and 150?

The memory bus is expected to stay at 400 MHz for Socket 754 Athlon 64 through Socket 939 Athlon 64 FX Toledo?

Starting with the Socket 939 Newcastle and continuing with Socket 939 Winchester and beyond, instead of the old two directional 800 MHz HyperTransport bus, there will be a two directional 1000 MHz HyperTransport bus?

What about Paris and Palermo?
 
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You have got it!!!

The current method of overclocking is to manipulate the memory clock.

The opterons (1xx, 2xx, 8xx) are all 800MHz hypertransport (and I suspect that the Opteron line will be the last to move to the 1GHz hypertransport) with the 8xx having all three hypertransport links enabled (for a total of six, one way 800MHz, 16 bit channels -- Just wait and see newegg list the 8xx Opterons as having a "4.8GHz fsb".) :D

I have no idea when AMD will choose to add support for higher speed memory. It was my understanding that ddr400 just recently became an official standard (rather than just a marketing label).

I have only one thing to say about Paris and Palermo: I have not been to either city...
 
Ha-ha.
I thought early Opterons used registered PC2700 not registered PC3200 RAM...
 
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