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Testing UTT and TCCD memory modules in Winchester and DFI NF4 Ultra-D setup
Hardware:
Winchester 3000+ (CBBHD 0447 UPCW)
XP 90, ~ 40 CFM fan (e.g. 90 mm Enermax)
DFI LP UT NF4 Ultra-D rev A02, bios 02/17/05
6600 GT overclocked to 1.19/0.59 GHz
Antec True 550W (using 20 pin connector + 4 pin 12 V connector)
Memory:
TCCD G. Skill PC4400 LE, 2 x 256 MB
TwinMOS UTT Speed Premium PC3200 (AA4T 44D week 0506(4)), 2 x 256 MB
No tweaking of the extended memory timing for both UTT and TCCD except tCL-tRCD-tRAS-tRP. Default values are used for the rest.
The extended timing in the bios is listed as follows (for both cases):
Ratio-Cmd-tCL-tRCD-tRAS-tRP-7-A-2-2-1-2-312-A-E-A-0-A-4-A-A-256-D-16-7-D
(A = Auto, E = Enable, D = Disable)
Table 1
CPU at 2772 MHz = 308.1 MHz x 9
UTT 2-2-2-5 1T 3.5 V, 252 MHz, 5:6 ratio, CPU / 11
TCCD 2.5-3-3-7 1T 2.9 V, 308 MHz, 1:1 ratio
................................... UTT ............ TCCD
3Dmark01 .......................... 23246/23371 .... 23349/23426
3Dmark03 .......................... 9971 ........... 9978
SuperPI 1M (sec) .................. 32 ............. 31
Everest Memory Read (MB/s) ........ 7155 ........... 8029
Everest Memory Write (MB/s) ....... 2277 ........... 2473
Everest Memory Latency (ns) ....... 37.3 ........... 35.5
Sandra CPU Integer MIPS ........... 12318 .......... 12311
Sandra Int Buff BW MB/s ........... 7323 (91%) ..... 7897 (80%)
SciMark2.0 MolecularDyn (sec) ..... 63.17 .......... 62.11
SciMark2.0 Primordia (sec) ........ 316.18 ......... 311.38
1.5-2-2-5 1T:
3Dmark01 23285
ScienceMark2.0 molecular dynamic 63.18 sec
Table 2
CPU at 2792 MHz = 310.3 MHz x 9
UTT 2-2-2-5 1T 3.5 V, 254 MHz, 5:6 ratio, CPU / 11
TCCD 2.5-3-3-7 1T 2.9 V, 310 MHz, 1:1 ratio
................................... UTT ............ TCCD
3Dmark01 .......................... 23409 .......... 23497
3Dmark03 .......................... 9951 ........... 9987
SuperPI 1M (sec) .................. 31 ............. 31
Everest Memory Read (MB/s) ........ 7149 ........... 8068
Everest Memory Write (MB/s) ....... 2282 ........... 2472
Everest Memory Latency (ns) ....... 37.3 ........... 36.1
Sandra CPU Integer MIPS ........... 12403 .......... 12402
Sandra Int Buff BW MB/s ........... 7387 (91%) ..... 7953 (80%)
SciMark2.0 MolecularDyn (sec) ..... 62.09 .......... 61.53
SciMark2.0 Primordia (sec) ........ 313.76 ......... 310.56
Table 3
CPU at 2799 MHz = 311.0 MHz x 9
UTT 1.5-2-2-5 1T 3.5 V, 255 MHz, 5:6 ratio, CPU / 11
TCCD 2.5-3-3-7 1T 2.9 V, 311 MHz, 1:1 ratio
................................... UTT ............ TCCD ........... TCCD (tRCD=4)
3Dmark01 .......................... 23396(?) ....... 23576 .......... 23217/23361 (to check these numbers)
3Dmark03 .......................... xxxx ........... 9980 ........... 9957
SuperPI 1M (sec) .................. 31 ............. 31 ............. 31
Everest Memory Read (MB/s) ........ 7220 ........... 8104 ........... 8012
Everest Memory Write (MB/s) ....... 2307 ........... 2493 ........... 2409
Everest Memory Latency (ns) ....... 37.0 ........... 35.1 ........... 36.7
Sandra CPU Integer MIPS ........... 12541 .......... 12434 .......... 12430
Sandra Int Buff BW MB/s ........... 7540 (93%) ..... 7987 (80%) ..... 7936 (80%)
SciMark2.0 MolecularDyn (sec) ..... 61.98 .......... 61.43 .......... 61.45
SciMark2.0 Primordia (sec) ........ 313.24 ......... 309.45 ......... 311.35
Other benchmarks, gaming scores may be added over time.
Summary of results:
Based on the runs of UTT at 252 MHz 2-2-2-5 1T and TCCD at 308 MHz 2.5-3-3-7 1T (22% higher frequency) in 3Dmark01, SuperPI, 3Dmark03, TCCD was about 100 point ahead in 3Dmark01 and 1 sec ahead in SuperPI 1M.
Also based on the runs of UTT at 255 MHz 1.5-2-2-5 1T and TCCD at 311 MHz 2.5-3-3-7 1T (22% higher frequency) in 3Dmark01, SuperPI, TCCD was about 100 point ahead in 3Dmark01 and tie in SuperPI 1M.
So within margin of error, by keeping the CPU, HTT, HT and video card frequencies the same, it is fair to say UTT at 2-2-2-5 1T ties with TCCD at 2.5-3-3-7 1T running at about 22% higher frequency, e.g. 255 MHz vs 311 MHz, based on the above program tests.
In another post (see link below) which estimated an upper bound for the tradeoff between memory frequency and latency:
In conjunction with the 30-42% for memory read of 1 to 8 burst, and the 33% typical based on analytical estimation by counting read access cycles (see link below), it is fair to establish that memory with 2.5-3-3-7 1T would need 25-30% higher bus frequency to break even with memory with 2-2-2-5 1T timing for memory performance in memory intensive applications.
From table 1, 2 and 3,
- 1 MHz of memory frequency at 2-2-2-5 is about 60-80 points in 3Dmark01.
- 1 cycle of tRCD is about 200-300 points in 3Dmark01 at 311 MHz
If motherboard and memory can run at 300+ MHz, TCCD would be more flexible to allow a wider range of frequency and timing for tweaking, with 2.8-2.9 V, from 2-2-2-5 1T at 200-220 MHz, to 2-3-2-6 1T at 240-250 MHz, to 2.5-3-3-7 1T at 280-310 MHz, to 2.5-4-3-8 1T at ~320 MHz, to 3-5-5-10 1T at ~350 MHz (not all TCCD can do this). And at such high frequency of about 20+% higher would tie the tight timing 2-2-2-5 1T of BH-5/UTT at 250-260 MHz.
If motherboard and memory can run only up to 250 - 300 MHz, and 3.3 - 3.5+ Vdimm is an option and is chosen to be used, then BH-5/UTT would be the choice (running at a ratio to HTT) as its tight timing 2-2-2-5 1T can catch up with the 20+% high frequency of TCCD running 2.5-3-3-7 1T.
But to run BH-5/UTT at 2-2-2-5 1T above 240 MHz, say 250 - 260 MHz, it would require 3.3+ V. I have some concerns about the long term reliability of using the 4V Vdimm option provided by the DFI NF4 boards due to the power/heat stress on the Vdimm regulator MOSFET (see few post down). For 24/7 usage for powering the BH-5/UTT, I would not use the 4V Vdimm option, but rather an addon memory booster to power the BH-5/UTT modules. A Vdimm booster may have the same problem depending on its exact circuitry, but at least it is not built into the board risking damaging the board.
But it is not clear whether the DFI NF4 boards would be compatible with Vdimm booster.
I have not used the memory booster, and I assume by using it, the current to the 3.3+ V BH-5/UTT would bypass the Vdimm regulator and hence would relieve the heat/power stress on the MOSFET and related components.
Memory frequency and latency tradeoff
How much frequency increase is needed to break-even with low latency
Hardware:
Winchester 3000+ (CBBHD 0447 UPCW)
XP 90, ~ 40 CFM fan (e.g. 90 mm Enermax)
DFI LP UT NF4 Ultra-D rev A02, bios 02/17/05
6600 GT overclocked to 1.19/0.59 GHz
Antec True 550W (using 20 pin connector + 4 pin 12 V connector)
Memory:
TCCD G. Skill PC4400 LE, 2 x 256 MB
TwinMOS UTT Speed Premium PC3200 (AA4T 44D week 0506(4)), 2 x 256 MB
No tweaking of the extended memory timing for both UTT and TCCD except tCL-tRCD-tRAS-tRP. Default values are used for the rest.
The extended timing in the bios is listed as follows (for both cases):
Ratio-Cmd-tCL-tRCD-tRAS-tRP-7-A-2-2-1-2-312-A-E-A-0-A-4-A-A-256-D-16-7-D
(A = Auto, E = Enable, D = Disable)
Table 1
CPU at 2772 MHz = 308.1 MHz x 9
UTT 2-2-2-5 1T 3.5 V, 252 MHz, 5:6 ratio, CPU / 11
TCCD 2.5-3-3-7 1T 2.9 V, 308 MHz, 1:1 ratio
................................... UTT ............ TCCD
3Dmark01 .......................... 23246/23371 .... 23349/23426
3Dmark03 .......................... 9971 ........... 9978
SuperPI 1M (sec) .................. 32 ............. 31
Everest Memory Read (MB/s) ........ 7155 ........... 8029
Everest Memory Write (MB/s) ....... 2277 ........... 2473
Everest Memory Latency (ns) ....... 37.3 ........... 35.5
Sandra CPU Integer MIPS ........... 12318 .......... 12311
Sandra Int Buff BW MB/s ........... 7323 (91%) ..... 7897 (80%)
SciMark2.0 MolecularDyn (sec) ..... 63.17 .......... 62.11
SciMark2.0 Primordia (sec) ........ 316.18 ......... 311.38
1.5-2-2-5 1T:
3Dmark01 23285
ScienceMark2.0 molecular dynamic 63.18 sec
Table 2
CPU at 2792 MHz = 310.3 MHz x 9
UTT 2-2-2-5 1T 3.5 V, 254 MHz, 5:6 ratio, CPU / 11
TCCD 2.5-3-3-7 1T 2.9 V, 310 MHz, 1:1 ratio
................................... UTT ............ TCCD
3Dmark01 .......................... 23409 .......... 23497
3Dmark03 .......................... 9951 ........... 9987
SuperPI 1M (sec) .................. 31 ............. 31
Everest Memory Read (MB/s) ........ 7149 ........... 8068
Everest Memory Write (MB/s) ....... 2282 ........... 2472
Everest Memory Latency (ns) ....... 37.3 ........... 36.1
Sandra CPU Integer MIPS ........... 12403 .......... 12402
Sandra Int Buff BW MB/s ........... 7387 (91%) ..... 7953 (80%)
SciMark2.0 MolecularDyn (sec) ..... 62.09 .......... 61.53
SciMark2.0 Primordia (sec) ........ 313.76 ......... 310.56
Table 3
CPU at 2799 MHz = 311.0 MHz x 9
UTT 1.5-2-2-5 1T 3.5 V, 255 MHz, 5:6 ratio, CPU / 11
TCCD 2.5-3-3-7 1T 2.9 V, 311 MHz, 1:1 ratio
................................... UTT ............ TCCD ........... TCCD (tRCD=4)
3Dmark01 .......................... 23396(?) ....... 23576 .......... 23217/23361 (to check these numbers)
3Dmark03 .......................... xxxx ........... 9980 ........... 9957
SuperPI 1M (sec) .................. 31 ............. 31 ............. 31
Everest Memory Read (MB/s) ........ 7220 ........... 8104 ........... 8012
Everest Memory Write (MB/s) ....... 2307 ........... 2493 ........... 2409
Everest Memory Latency (ns) ....... 37.0 ........... 35.1 ........... 36.7
Sandra CPU Integer MIPS ........... 12541 .......... 12434 .......... 12430
Sandra Int Buff BW MB/s ........... 7540 (93%) ..... 7987 (80%) ..... 7936 (80%)
SciMark2.0 MolecularDyn (sec) ..... 61.98 .......... 61.43 .......... 61.45
SciMark2.0 Primordia (sec) ........ 313.24 ......... 309.45 ......... 311.35
Other benchmarks, gaming scores may be added over time.
Summary of results:
Based on the runs of UTT at 252 MHz 2-2-2-5 1T and TCCD at 308 MHz 2.5-3-3-7 1T (22% higher frequency) in 3Dmark01, SuperPI, 3Dmark03, TCCD was about 100 point ahead in 3Dmark01 and 1 sec ahead in SuperPI 1M.
Also based on the runs of UTT at 255 MHz 1.5-2-2-5 1T and TCCD at 311 MHz 2.5-3-3-7 1T (22% higher frequency) in 3Dmark01, SuperPI, TCCD was about 100 point ahead in 3Dmark01 and tie in SuperPI 1M.
So within margin of error, by keeping the CPU, HTT, HT and video card frequencies the same, it is fair to say UTT at 2-2-2-5 1T ties with TCCD at 2.5-3-3-7 1T running at about 22% higher frequency, e.g. 255 MHz vs 311 MHz, based on the above program tests.
In another post (see link below) which estimated an upper bound for the tradeoff between memory frequency and latency:
In conjunction with the 30-42% for memory read of 1 to 8 burst, and the 33% typical based on analytical estimation by counting read access cycles (see link below), it is fair to establish that memory with 2.5-3-3-7 1T would need 25-30% higher bus frequency to break even with memory with 2-2-2-5 1T timing for memory performance in memory intensive applications.
From table 1, 2 and 3,
- 1 MHz of memory frequency at 2-2-2-5 is about 60-80 points in 3Dmark01.
- 1 cycle of tRCD is about 200-300 points in 3Dmark01 at 311 MHz
If motherboard and memory can run at 300+ MHz, TCCD would be more flexible to allow a wider range of frequency and timing for tweaking, with 2.8-2.9 V, from 2-2-2-5 1T at 200-220 MHz, to 2-3-2-6 1T at 240-250 MHz, to 2.5-3-3-7 1T at 280-310 MHz, to 2.5-4-3-8 1T at ~320 MHz, to 3-5-5-10 1T at ~350 MHz (not all TCCD can do this). And at such high frequency of about 20+% higher would tie the tight timing 2-2-2-5 1T of BH-5/UTT at 250-260 MHz.
If motherboard and memory can run only up to 250 - 300 MHz, and 3.3 - 3.5+ Vdimm is an option and is chosen to be used, then BH-5/UTT would be the choice (running at a ratio to HTT) as its tight timing 2-2-2-5 1T can catch up with the 20+% high frequency of TCCD running 2.5-3-3-7 1T.
But to run BH-5/UTT at 2-2-2-5 1T above 240 MHz, say 250 - 260 MHz, it would require 3.3+ V. I have some concerns about the long term reliability of using the 4V Vdimm option provided by the DFI NF4 boards due to the power/heat stress on the Vdimm regulator MOSFET (see few post down). For 24/7 usage for powering the BH-5/UTT, I would not use the 4V Vdimm option, but rather an addon memory booster to power the BH-5/UTT modules. A Vdimm booster may have the same problem depending on its exact circuitry, but at least it is not built into the board risking damaging the board.
But it is not clear whether the DFI NF4 boards would be compatible with Vdimm booster.
I have not used the memory booster, and I assume by using it, the current to the 3.3+ V BH-5/UTT would bypass the Vdimm regulator and hence would relieve the heat/power stress on the MOSFET and related components.
Memory frequency and latency tradeoff
How much frequency increase is needed to break-even with low latency
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