1. If you want the technical details, the quad-pumped bus is controlled by 4 positive (P) and 4 negative (N) strobe signals. The strobe signals basically run at twice the rate of the bus clock (so if the bus clock is 100MHz, the strobe signals run at 200Mhz). Data is transferred on the rising edge of either a P or N strobe, so that effectively gives you 4x the bus clock. Each strobe is tied to 16 of the data pins (4 groups of 16 pins = the 64-bit wide bus). The P4 address bus is only double-pumped however.
More details are available in the P4 datasheet on Intel's website.
2. As far as I know, RDRAM is very high speed, narrow-bus single data rate memory. In other words, one DDR200 module transfers 64 bits twice per clock at 100Mhz for a total of 1.6GB/s, while an RDRAM module transfers 16 bits once per clock at 800Mhz for a total of 1.6GB/s. Both have the same theoretical performance.
For a while some companies were trying to come out with quad-band memory (QBM). It was similar to quad-pumped in that it could transfer data at 4x the clock, but the industry was already headed in the direction of DDR2 and QBM didn't offer a compelling performance advantage. It might still turn up in niche markets though.
3. The performance of the qual-pumped bus is realized with dual channel memory. This is true for both RDRAM and DDR-RAM. Generally, it takes two memory channels to saturate the P4's bus. That's why DDR400 and 800Mhz FSB chips are such a common pairing these days. Of course in practice the theoretical performance of both the bus and the RAM is not reached.
